vunit_defines.svh
everything in it except CHECK_EQUAL
can be considered part of the core functionality. The CHECK_EQUAL
should be moved to a separate check
library which together with other convenient check-functions. The core functionality might be possible to implement in pure Verilog and but the check library might be SystemVerilog-only. That way Verilog-only simulators can still use the test-automation features of VUnit without benefiting from convenient check-functions.setup
and the pass/fail mechanism. Basically the Python part of VUnit sets a runner_cfg
generic that is a string in a certain format that contains a number of fields such as the test case to run and the output path. This string needs to be parsed in setup for the HDL-part of VUnit to now which if run('test_name')
if statement(s) it should go into. The pass/fail mechanism is through writing the $output_path/vunit_results
file. A pass is when the simulation ends with the correct contents in vunit_results
file and a fail is a (premature) simulation ending without the correct results written into vunit_results
. Basically if the simulation ends before reaching cleanup
it is considered a fail.